In a semiconductor memory structure, there are typically two pattern features in the cell area. One feature is a large gate pattern which is usually rectangular. The large pattern can be configured as a ground select line (GSL) or a string select line (SSL). Another feature includes a plurality of fine gate lines arranged in an array manner. The fine gate lines are configured as word lines located between the large patterns.
The large patterns act as a switch to turn on/off the fine gate lines is array in between, while the distance between the large pattern and the gate lines is a critical dimension to fabricate the memory structure. Typically, the characterization of the large pattern and the fine gate lines array is accomplished at a different stage, with the distance between these two features being dependant on the alignment accuracy from stage to stage. Unfortunately, alignment shifting is an unavoidable factor that must be assessed during the semiconductor manufacturing process. Thus, the distance between these two features may vary according to the shift direction of a stage-to-stage offset. Some large patterns may be closer to the fine gate lines, as desired, and if the distance is shorter to a nominal value requested by the circuit designer, the memory performance may be degraded. A hot carrier, for example, may break down the memory device.
Therefore, the distance between the large pattern (for example, SSL or GSL) and its nearest fine gate line (for example, word line) needs to be a predetermined value as required. And the distance should not be vulnerable to the alignment shift or any process deviation.